###############################################################################
## @copyright Copyright (c) 2022 OnMicro Corp.
## @brief     Cortex-M0 SoC demo on OnMicro FPGA han325t.
## @author    admin@ultra-embedded.com
##            wei.lu@onmicro.com.cn enhancment on 2022/09
## @license   SPDX-License-Identifier: Apache-2.0
###############################################################################
PART_NAME    = xc7k325t
PART_PACKAGE = ffg900
PART_SPEED   = 1

CPU         ?= cortex-m0

# Choice: [rv32i, rv32i_spartan6, rv32im, rv32imsu]
RISCV_CORE  ?= rv32im

SRC_DIR      = .
SRC_DIR     += ../han325t
SRC_DIR     += ../common/ue_soc
SRC_DIR     += ../../ip/connectivity/ue_uart2mem/src_v
SRC_DIR     += ../../ip/connectivity/uart_lite/src_v
SRC_DIR     += ../../ip/connectivity/spi_lite/src_v
SRC_DIR     += ../../ip/peripheral/ue_intc/src_v
SRC_DIR     += ../../ip/peripheral/ue_gpio/src_v
SRC_DIR     += ../../ip/peripheral/ue_timer/src_v
SRC_DIR     += ../../ip/bus/ue_axi4lite/src_v
SRC_DIR     += ../../ip/bus/ue_bridge_axi4_axi4lite/src_v

# RISC-V
ifeq ($(CPU),riscv)
  SRC_DIR      += ../../ip/cpu/ue_$(RISCV_CORE)/src_v
  SRC_DIR      += ../../ip/cpu/ue_riscv_tcm/src_v
  EXTRA_VFLAGS += CPU_SELECT_RISCV=1
else
  # Cortex M0
  SRC_DIR      += ../../ip/cpu/cortex_m0/src_v
  SRC_DIR      += ../../ip/cpu/ue_cm0_tcm/src_v
  EXTRA_VFLAGS += CPU_SELECT_ARMV6M=1
endif

include ../common/Makefile.fpga_vivado
